AD9175 datasheet(118/150 Pages) AD

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AD9175

Data Sheet

Rev. A | Page 118 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x32E

SHORT_TPL_TEST_2

[7:0]

SHORT_TPL_REF_

SP_MSB

Short transport layer test reference sample,

MSB. This bit field is the upper eight bits of

the expected DAC sample during the short

transport layer test and is used to compare

with the received sample at the JESD204B

receiver output.

0x0

R/W

0x32F

SHORT_TPL_TEST_3

SHORT_TPL_LINK_

SEL

For running STPL on dual-link JESD204B

modes. Selects whether the STPL test is

performed on samples that are addressed

to the DAC0 channelizers/datapaths (Link 0),

or the DAC1 channelizers/datapaths

(Link 1).

0x0

R/W

Link 0 samples are tested.

Link 1 samples are tested.

SHORT_TPL_IQ_

SAMPLE_SEL

Selects which data stream (path) to test for

a complex subchannel of the channelizer, I

or Q. For nonIQ JESD204B modes, select the

I path.

0x0

R/W

Select to test the I data stream.

Select to test the Q data stream.

[5:1]

RESERVED

Reserved.

0x0

R/W

SHORT_TPL_FAIL

Short transport layer test fail. This bit shows

if the selected DAC sample matches the

expected sample for the short transport

layer test. If they match, the test passes.

Otherwise, the test fails.

0x0

Test pass.

Test fail.

0x334

JESD_BIT_INVERSE_

CTRL

[7:0]

JESD_BIT_INVERSE

Logical lane invert. Each bit of this control

inverses the JESD204B deserialized data

from one specific JESD204B receiver PHY.

Set Bit x high to invert the JESD204B

deserialized data on Logical Lane x.

0x0

R/W

0x400

DID_REG

[7:0]

DID_RD

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

0x401

BID_REG

[7:0]

BID_RD

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

0x402

LID0_REG

RESERVED

Reserved.

0x0

ADJDIR_RD

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

PHADJ_RD

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

[4:0]

LL_LID0

Received ILAS LID configuration on Lane 0.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

0x403

SCR_L_REG

SCR_RD

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

Scrambling is disabled.

Scrambling is enabled.

[6:5]

RESERVED

Reserved.

0x0

[4:0]

L_RD_1

Received ILAS configuration on Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

AD9175 Datasheet(PDF) 118 Page - Analog Devices

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