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C161 Datasheet(PDF) 270 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 270 Page - Infineon Technologies AG |
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270 / 400 page  &3, 7KH5HDO 7LPH &ORFN User’s Manual 14-2 1999-08 Figure 14-2 RTC Block Diagram System Clock Operation A real time system clock can be maintained that keeps on running also during idle mode and power down mode (optionally) and represents the current time and date. This is possible as the RTC module is not effected by a reset. The maximum resolution (minimum stepwidth) for this clock information is determined by timer T14’s input clock. The maximum usable timespan is achieved when T14REL is loaded with 0000 H and so T14 divides by 2 16. Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever timer T14 overflows and is reloaded. This interrupt request may e.g. be used to provide a system time tick independent of the CPU frequency without loading the general purpose timers, or to wake up regularly from idle mode. The interrupt cycle time can be adjusted via the timer T14 reload register T14REL. Please refer to „RTC Interrupt Generation“ below for more details. 48-bit Timer Operation The concatenation of the 16-bit reload timer T14 and the 32-bit RTC timer can be regarded as a 48-bit timer which is clocked with the RTC input frequency divided by the fixed prescaler. The reload register T14REL should be cleared to get a 48-bit binary timer. However, any other reload value may be used. The maximum usable timespan is 2 48 ( ≈1014) T14 input clocks, which would equal more than 100 years at an oscillator frequency of 20 MHz. RTCL RTCH T14 T14REL 8:1 f RTC Reload Interrupt Request |
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