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C161 Datasheet(PDF) 271 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 271 Page - Infineon Technologies AG |
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271 / 400 page  &3, 7KH5HDO 7LPH &ORFN User’s Manual 14-3 1999-08 RTC Register Access The actual value of the RTC is represented by the 3 registers T14, RTCL and RTCH. As these registers are concatenated to build the RTC counter chain, internal overflows occur while the RTC is running. When reading or writing the RTC value make sure to account for such internal overflows in order to avoid reading/writing corrupted values. When reading/writing e.g. 0000 H to RTCH and then accessing RTCL will produce a corrupted value as RTCL may overflow before it can be accessed. In this case, however, RTCH would be 0001 H. The same precautions must be taken for T14 and T14REL. RTC Interrupt Generation The RTC interrupt shares the XPER3 interrupt node with the PLL/OWD interrupt (if available). This is controlled by the interrupt subnode control register ISNC. The interrupt handler can determine the source of an interrupt request via the separate interrupt request and enable flags (see figure below) provided in register ISNC. Note: If only one source is enabled no additional software check is required, of course. Figure 14-3 RTC Interrupt Logic If T14 interrupts are to be used both stages, the interrupt node (XP3IE=’1’) and the RTC subnode (RTCIE=’1’) must be enabled. Please note that the node request bit XP3IR is automatically cleared when the interrupt handler is vectored to, while the subnode request bit RTCIR must be cleared by software. PLL/OWD Interrupt Intr.Request 1) Intr.Enable 1) PLLIR PLLIE Intr.Request Intr.Enable RTCIR RTCIE T14 Interrupt XPER3 Interrupt Node Interrupt Controller Note: 1) Only available if PLL is implemented Register XP3IC Register ISNC |
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