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C161 Datasheet(PDF) 162 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 162 Page - Infineon Technologies AG |
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162 / 400 page  &3, 'HGLFDWHG 3LQV User’s Manual 8-2 1999-08 The External Read Strobe RD controls the output drivers of external memory or peripherals when the C161PI reads data from these external devices. During accesses to on-chip X-Peripherals RD remains inactive (high). During reset an internal pullup ensures an inactive (high) level on the RD output. The External Write Strobe WR/WRL controls the data transfer from the C161PI to an external memory or peripheral device. This pin may either provide an general WR signal activated for both byte and word write accesses, or specifically control the low byte of an external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/ BHE). During accesses to on-chip X-Peripherals WR/WRL remains inactive (high). During reset an internal pullup ensures an inactive (high) level on the WR/WRL output. The Ready Input READY receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle, provided that this function is enabled for the current bus cycle. READY may be used as synchronous READY or may be evaluated asynchronously. When waitstates are defined for a READY controlled address window the READY input is not evaluated during these waitstates. An internal pullup ensures an inactive (high) level on the READY input. The External Access Enable Pin EA determines if the C161PI after reset starts fetching code from the internal ROM area (EA=’1’) or via the external bus interface (EA=’0’). Be sure to hold this input low for ROMless devices. At the end of the internal reset sequence the EA signal is latched together with the PORT0 configuration. The Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal (e.g. a power-fail signal). It also serves to validate the PWRDN instruction that switches the C161PI into Power-Down mode. The NMI pin is sampled with every CPU clock cycle to detect transitions. The Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the external crystal. The oscillator provides an inverter and a feedback element. The standard external oscillator circuitry (see chapter „Clock Generation“) comprises the crystal, two low end capacitors and series resistor to limit the current through the crystal. An external clock signal may be fed to the input XTAL1, leaving XTAL2 open or terminating it for higher input frequencies. |
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