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C161 Datasheet(PDF) 249 Page - Infineon Technologies AG

Part # C161
Description  16-Bit Single-Chip Microcontroller
PDF  400 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C161 Datasheet(HTML) 249 Page - Infineon Technologies AG

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User’s Manual
12-3
1999-08
SSCCON
SSC Control Reg. (Pr.M.)
SFR (FFB2
H/D9H)
Reset value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSC
EN
=0
SSC
MS
-
SSC
AR
EN
SSC
BEN
SSC
PEN
SSC
REN
SSC
TEN
-
SSC
PO
SSC
PH
SSC
HB
SSCBM
rw
rw
-
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit
Function (Programming Mode, SSCEN = ‘0’)
SSCBM
SSC Data Width Selection
0:
Reserved. Do not use this combination.
1..15: Transfer Data Width is 2...16 bit (<SSCBM>+1)
SSCHB
SSC Heading Control Bit
0:
Transmit/Receive LSB First
1:
Transmit/Receive MSB First
SSCPH
SSC Clock Phase Control Bit
0:
Shift transmit data on the leading clock edge, latch on trailing edge
1:
Latch receive data on leading clock edge, shift on trailing edge
SSCPO
SSC Clock Polarity Control Bit
0:
Idle clock line is low, leading clock edge is low-to-high transition
1:
Idle clock line is high, leading clock edge is high-to-low transition
SSCTEN
SSC Transmit Error Enable Bit
0:
Ignore transmit errors
1:
Check transmit errors
SSCREN
SSC Receive Error Enable Bit
0:
Ignore receive errors
1:
Check receive errors
SSCPEN
SSC Phase Error Enable Bit
0:
Ignore phase errors
1:
Check phase errors
SSCBEN
SSC Baudrate Error Enable Bit
0:
Ignore baudrate errors
1:
Check baudrate errors
SSCAREN
SSC Automatic Reset Enable Bit
0:
No additional action upon a baudrate error
1:
The SSC is automatically reset upon a baudrate error
SSCMS
SSC Master Select Bit
0:
Slave Mode. Operate on shift clock received via SCLK.
1:
Master Mode. Generate shift clock and output it via SCLK.
SSCEN
SSC Enable Bit = ‘0’
Transmission and reception disabled. Access to control bits.



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