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82830MP Datasheet(PDF) 71 Page - Intel Corporation |
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82830MP Datasheet(HTML) 71 Page - Intel Corporation |
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71 / 159 page ![]() Intel ® 830MP Chipset 298338-001 Datasheet 71 R 4.5.1.25 ESMRAMC - Extended System Management RAM Control Register - Device #0 Address Offset: 91h Default Value: 38h Access: Read/Write Size: 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. Bit Description 7 H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e. above 1 MB or below 1MB) When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory space is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to SDRAM address 000A0000h to 000BFFFFh. Once D_LCK is set, this bit becomes read only. Default Value=0. 6 E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it Default Value=0. 5 SMRAM_Cache (SM_CACHE): This bit is forced to ‘1’ by the GMCH-M . Default Value=1. 4 SMRAM_L1_EN (SM_L1): This bit is forced to ‘1’ by the GMCH-M. Default Value=1. 3 SMRAM_L2_EN (SM_L2): This bit is forced to ‘1’ by the GMCH-M. Default Value=1. 2 Reserved 1 TSEG_SZ(T_SZ): Selects the size of the TSEG memory block if enabled. This memory is taken from the top of SDRAM space (i.e. TOM - TSEG_SZ), which is no longer claimed by the memory controller. This field decodes as follows: TSEG_SZ Description 0 (TOM-512K) to TOM 1 (TOM-1M) to TOM Once D_LCK is set, this bit becomes read only. Default Value=0. 0 TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 512 Kbytes or 1 Mbytes of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only. Default Value=0. |
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