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82830MP Datasheet(PDF) 29 Page - Intel Corporation

Part # 82830MP
Description  Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)
PDF  159 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82830MP Datasheet(HTML) 29 Page - Intel Corporation

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Intel
® 830MP Chipset
298338-001
Datasheet
29
R
3.5
Clocking and Reset
Table 10. Clocking and Reset Signal Descriptions
Signal Name
Type
Description
HTCLK;
HTCLK#
I
CMOS
Host Clock In: These pins receive a buffered host clock from the external clock
synthesizer. This clock is used by all of the GMCH-M. The clock is also the reference
clock for the graphics core PLL. This is a low voltage differential input.
GBOUT
O
CMOS
AGP/Hub Clock Reference Output: This clock goes to the external AGP/Hub/PCI
buffer.
GBIN
I
CMOS
AGP/Hub Input Clock: 66 MHz, 3.3-V input clock from external buffer AGP/Hub-link
interface.
GM_GCLK;
GM_RCLK
O
CMOS
Reserved
DCLKREF
I
LVTTL
Reserved
RESET#
I
LVTTL
Reset In: When asserted, this signal will asynchronously reset the GMCH-M logic.
This signal is connected to the PCIRST# output of the ICH3-M. The ICH3-M drives this
to 3.3V. All AGP/PCI output and bi-directional signals will also tri-state compliant to
PCI rev 2.2 specifications. This input should have a Schmidt trigger to avoid spurious
resets. Note that this input needs to be 3.3-V tolerant.
Total pins for Clocks/Resets section: 8.



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