82830MP datasheet(23/159 Pages) INTEL

23 / 159 page

Intel

® 830MP Chipset

298338-001

Datasheet

3.3

AGP Interface Signals

3.3.1

AGP Addressing Signals

Table 4. AGP Addressing Signal Descriptions

Signal

Name

Type

Description

PIPE#

AGP

Pipelined Read: This signal is asserted by the current master to indicate a full width

address is to be queued by the target. The master queues one request each rising clock

edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued

across the AD bus. PIPE# is a sustained tri-state signal from the master (graphics

controller) and is an input to the GMCH-M.

SBA[7:0]

AGP

Sideband Address: This bus provides an additional bus to pass address and command

to the GMCH-M from the AGP master.

The above table contains two mechanisms to queue requests by the AGP master. Note that the master

can only use one mechanism. When PIPE# is used to queue addresses, the master is not allowed to

queue addresses using the SBA bus. For example, during configuration time, if the master indicates that

it can use either mechanism, the configuration software will indicate which mechanism the master will

use. Once this choice has been made, the master will continue to use the mechanism selected until the

master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic

mechanism but rather a static decision when the device is first being configured after reset.

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