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82830MP Datasheet(PDF) 46 Page - Intel Corporation |
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82830MP Datasheet(HTML) 46 Page - Intel Corporation |
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46 / 159 page ![]() Intel ® 830MP Chipset 46 Datasheet 298338-001 R 4.5.1 SDRAM Controller/Host-hub Interface Device Registers - Device #0 Table 19 shows the GMCH-M configuration space for device #0. An “s” in the Default Value field means that a strap determines the power-up default value for that bit. Table 19. Host-Hub I/F Bridge/SDRAM Controller Configuration Space (Device #0) Address Offset Register Symbol Register Name Default Value Access 00-01h VID Vendor Identification 8086h RO 02-03h DID Device Identification 3575h RO 04-05h PCICMD PCI Command Register 0006h R/W 06-07h PCISTS PCI Status Register 0010h RO, R/WC 08h RID Revision Identification 00h RO 09h - Intel Reserved - - 0Ah SUBC Sub-Class Code 00h RO 0Bh BCC Base Class Code 06h RO 0Ch - Intel Reserved - - 0Dh MLT Master Latency Timer 00h RO 0Eh HDR Header Type 00h RO 0Fh - Intel Reserved - - 10-13h APBASE Aperture Base Configuration 00000008h R/W, RO 14-2Bh - Intel Reserved - - 2C-2Dh SVID Subsystem Vendor Identification 00h R/WO 2E-2Fh SID Subsystem Identification 00h R/WO 30-33h - Intel Reserved - - 34h CAPPTR Capabilities Pointer 40h RO 35-3Fh - Intel Reserved - - 40-44h - Intel Reserved - - 45-47h - Intel Reserved - - 48-4Bh RRBAR Register Range Base Address 00000000h R/W, RO 4C-4Fh - Intel Reserved - - 50-51h GCC0 GMCH Control Register 0 A072h R/W, RO 52-53h GCC1 GMCH Control Register 1 0000h R/W 54-55h - Intel Reserved - - 56-57h - Intel Reserved - - 58h FDHC Fixed DRAM Hole Control 00h R/W 59-5Fh PAM[6:0] Programmable Attribute Map (7 registers) 00h R/W |
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