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82830MP Datasheet(PDF) 4 Page - Intel Corporation

Part # 82830MP
Description  Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)
PDF  159 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82830MP Datasheet(HTML) 4 Page - Intel Corporation

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Intel
® 830MP Chipset
4
Datasheet
298338-001
R
4.5.1.5
RID - Revision Identification Register - Device #0 ......................... 51
4.5.1.6
SUBC - Sub-Class Code Register - Device #0 .............................. 51
4.5.1.7
BCC - Base Class Code Register - Device #0 ............................... 51
4.5.1.8
MLT - Master Latency Timer Register - Device #0......................... 52
4.5.1.9
HDR - Header Type Register - Device #0 ...................................... 52
4.5.1.10
APBASE - Aperture Base Configuration Register - Device #0...... 53
4.5.1.11
SVID - Subsystem Vendor ID - Device #0..................................... 54
4.5.1.12
SID - Subsystem ID - Device #0.................................................... 54
4.5.1.13
CAPPTR - Capabilities Pointer - Device #0 .................................. 54
4.5.1.14
RRBAR - Register Range Base Address Register - Device #0 ..... 55
4.5.1.15
GCC0 - GMCH Control Register #0 - Device #0 ............................ 56
4.5.1.16
GCC1-–GMCH Control Register #1 - Device #0 ............................ 58
4.5.1.17
FDHC - Fixed DRAM Hole Control Register - Device #0 ............... 58
4.5.1.18
PAM(6:0) - Programmable Attribute Map Registers - Device #0 ... 59
4.5.1.19
DRB — DRAM Row Boundary Register - Device #0 ..................... 62
4.5.1.20
DRA — DRAM Row Attribute Register - Device #0 ....................... 63
4.5.1.21
DRT—DRAM Timing Register - Device #0 .................................... 64
4.5.1.22
DRC - DRAM Controller Mode Register - Device #0...................... 66
4.5.1.23
DTC - DRAM Throttling Control Register - Device #0. ................... 68
4.5.1.24
SMRAM - System Management RAM Control Register - Device #070
4.5.1.25
ESMRAMC - Extended System Management RAM Control
Register - Device #0 ....................................................................... 71
4.5.1.26
ERRSTS – Error Status Register – Device #0 ............................... 72
4.5.1.27
ERRCMD - Error Command Register - Device #0 ......................... 73
4.5.1.28
ACAPID - AGP Capability Identifier Register - Device #0.............. 75
4.5.1.29
AGPSTAT - AGP Status Register - Device #0 ............................... 76
4.5.1.30
AGPCMD - AGP Command Register - Device #0.......................... 77
4.5.1.31
AGPCTRL - AGP Control Register - Device #0 ............................. 78
4.5.1.32
AFT – AGP Functional Test Register – Device #0 ......................... 78
4.5.1.33
APSIZE
 Aperture Size - Device #0 ............................................. 78
4.5.1.34
ATTBASE
 Aperture Translation Table Base Register - Device #079
4.5.1.35
AMTT
AGP Interface Multi-Transaction Timer Register - Device
#0 .................................................................................................. 79
4.5.1.36
LPTT
Low Priority Transaction Timer Register - Device #0 ........ 80
4.5.1.37
BUFF_SC – System Memory Buffer Strength Control Register -
Device #0........................................................................................ 81
4.5.1.37.1
SDR Drive Strength Register Description .................... 81
4.5.2
HOST-AGP Bridge Registers - Device #1................................................... 84
4.5.2.1
VID1 - Vendor Identification Register - Device #1.......................... 85
4.5.2.2
DID1 - Device Identification Register - Device #1 .......................... 85
4.5.2.3
PCICMD1 - PCI-PCI Command Register - Device #1.................... 86
4.5.2.4
PCISTS1 - PCI-PCI Status Register - Device #1 ........................... 87
4.5.2.5
RID1 - Revision Identification Register - Device #1 ....................... 87
4.5.2.6
SUBC1 - Sub-Class Code Register - Device #1 ............................ 88
4.5.2.7
BCC1 - Base Class Code Register - Device #1 ............................. 88
4.5.2.8
MLT1 - Master Latency Timer Register - Device #1....................... 88
4.5.2.9
HDR1 - Header Type Register - Device #1 .................................... 89
4.5.2.10
PBUSN - Primary Bus Number Register - Device #1..................... 89
4.5.2.11
SBUSN - Secondary Bus Number Register - Device #1............... 89
4.5.2.12
SUBUSN - Subordinate Bus Number Register - Device #1 ........... 90
4.5.2.13
SMLT - Secondary Master Latency Timer Register - Device #1.... 90
4.5.2.14
IOBASE - I/O Base Address Register - Device #1 ......................... 91
4.5.2.15
IOLIMIT - I/O Limit Address Register - Device #1 .......................... 91
4.5.2.16
SSTS - Secondary PCI-PCI Status Register - Device #1.............. 92



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