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AX58200 Datasheet(PDF) 27 Page - ASIX Electronics Corporation |
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AX58200 Datasheet(HTML) 27 Page - ASIX Electronics Corporation |
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27 / 180 page  27 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC Pin No Pin Name Type MFP Description I2C1_SMBSUS O MFP8 I2C1 SMBus SMBSUS pin (PMBus CONTROL pin) I2C2_SDA I/O MFP9 I2C2 data input/output pin. UART1_RXD I MFP10 UART1 data receiver input pin. A11 HSUSB_VDD12_CAP A MFP0 HSUSB Internal power regulator output 1.2V decoupling pin. Note: This pin needs to be connected with a 1uF capacitor. A12 HSUSB_D+ A MFP0 HSUSB differential signal D+. B11 HSUSB_ID I MFP0 HSUSB identification. B12 HSUSB_D- A MFP0 HSUSB differential signal D-. C11 HSUSB_VBUS P MFP0 HSUSB Power supply from USB host or HUB. C12 HSUSB_VRES A MFP0 HSUSB module reference resister D11 HSUSB_VSS P MFP0 Ground pin for HSUSB. D12 HSUSB_VDD33 P MFP0 Power supply for HSUSB VDD33 1.4.2 ESC Sub-system Pin Description The multi-function pin settings are configured by the I2C Hardware Configuration EEPROM (HWCFGEE). Please refer to Section 2.43.4.2 for details. Pin No Pin Name Type MFP Description D9 TEST I5/PD/S Test mode enable For normal operation, please always tie to logic low or NC. C10 RSTn I5/PU/S Reset Input, active low RST_N is the hardware reset input used to reset this chip. This input is AND with internal Power- On-Reset (POR) circuit, which generates the main system reset for this chip. E9 RSTO\ RSTO_POL O5/8m Reset Output This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the RSTO polarity, please refer to Section 2.43.4.1. F9 NC I3 Reserved. Please connect to GND. L1 LED_RUN\ EEP_SIZE B5/4m RUN LED This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the EEPROM size configuration, please refer to Section 2.43.4.1. L2 LED_ERR\ 3PORT_MODE B5/4m Error LED This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the Port 2 MII enable configuration, please refer to Section 2.43.4.1. J10 P0_ACT\ P0_FIBER B5/4m PHY 0 Link/Activity LED This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the PHY 0 media mode, please refer to Section 2.43.4.1. J11 P1_ACT\ P1_FIBER B5/4m PHY 1 Link/Activity LED This pin is input direction during chip reset stage |
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