AX58200 datasheet(54/180 Pages) ASIX

54 / 180 page

AX58200

EtherCAT Slave Controller SoC

2.2.11 System Timer (SysTick)

The Cortex® -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write,

decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time

Operating System (RTOS) tick timer or as a simple counter.

When system timer is enabled, it will count down from the value in the SysTick Current Value Register

(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on

the next clock cycle, and then decrement on subsequent clocks. When the counter transitions to 0, the

COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.

The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero before

enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than an arbitrary value

when it is enabled.

If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded with this

value. This mechanism can be used to disable the feature independently from the timer enable bit.

For more detailed information, please refer to the “ARM® Cortex® -M4 Technical Reference Manual” and “ARM®

v6-M Architecture Reference Manual”.

2.2.12 Nested Vectored Interrupt Controller (NVIC)

The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and

efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts

to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can cause

interrupts to enter a pending state in user mode if you enable the Configuration and Control Register. Any other

user mode access causes a bus fault. You can access all NVIC registers using byte, halfword, and word accesses

unless otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC registers

and system debug registers are little-endian regardless of the endianness state of the processor.

The NVIC supports:

⚫

An implementation-defined number of interrupts, in the range 1-240 interrupts.

⚫

A programmable priority level of 0-16 for each interrupt; a higher level corresponds to a lower

priority, so level 0 is the highest interrupt priority.

⚫

Level and pulse detection of interrupt signals.

⚫

Dynamic reprioritization of interrupts.

⚫

Grouping of priority values into group priority and subpriority fields.

⚫

Interrupt tail-chaining.

⚫

An external Non Maskable Interrupt (NMI)

⚫

WIC with Ultra-low Power Sleep mode support

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no

instruction overhead. This provides low latency exception handling.

AX58200 Datasheet(PDF) 54 Page - ASIX Electronics Corporation

AX58200 Datasheet(HTML) 54 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL