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AX58200 Datasheet(PDF) 34 Page - ASIX Electronics Corporation

Part # AX58200
Description  EtherCAT Slave Controller SoC
PDF  180 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX58200 Datasheet(HTML) 34 Page - ASIX Electronics Corporation

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Copyright © 2019 ASIX Electronics Corporation. All rights reserved.
AX58200
EtherCAT Slave Controller SoC
debug control registers even while SYSRESETn is asserted.
–
Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug access
–
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code
patches
–
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data
tracing, and system profiling
–
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging
–
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA),
including Single Wire Output (SWO) mode
–
Optional Embedded Trace Macrocell (ETM) for instruction trace.
⚫
Bus interfaces:
–
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, and
System bus interfaces
–
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
–
Bit-band support that includes atomic bit-band write and read operations.
–
Memory access alignment
–
Write buffer for buffering of write data
–
Exclusive access transfers for multiprocessor systems



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