AX58200 datasheet(50/180 Pages) ASIX

50 / 180 page

AX58200

EtherCAT Slave Controller SoC

When setting the control register CCMEN(SPIM_CTL1[2]) to 0, SRAM bank2 is switched to external SPI Flash

cache memory. In this case, the SRAM bank2 can’t be accessed as general SRAM. If user access SRAM bank2

by AHB bus master, the SPI Flash controller will send error response via HRESP AHB bus signal to bus master.

32K byte

SRAM bank0

0x2000_0000

Reserved

0x3FFF_FFFF

96K byte

SRAM bank1

0x2000_7FFF

0x2002_7FFF

0x2000_8000

0x2002_8000

160K byte device

32K byte

SRAM bank0

0x1000_0000

96K byte

SRAM bank1

0x1000_7FFF

0x1001_FFFF

0x1000_8000

160K byte device

remapping

32K byte

SRAM bank2

0x2001_FFFF

0x2002_0000

0x1002_7FFF

32K byte

SRAM bank2

0x1002_0000

remapping

Figure 2.2-10: SRAM Memory Organization

SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the parity error checking

mechanism is dynamic operating. As parity error occurred, the PERRIF (SYS_SRAM_STATUS[0]) will be

asserted to 1 and the SYS_SRAM_ERRADDR register will recode the address with parity error. Chip will enter

interrupt when SRAM parity error occurred if PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. When SRAM

parity error occurred, chip will stop detecting SRAM parity error until user writes 1 to clear the

PERRIF(SYS_SRAM_STATUS[0]) bit.

2.2.8

Bus Matrix

The AX58200 supports Bus Matrix to manage the access arbitration between masters. The access arbitration can

be selected by INTACTEN (SYS_AHBMCTL[0]) to use round-robin algorithm or set Cortex® -M4 CPU as the

highest bus priority.

AX58200 Datasheet(PDF) 50 Page - ASIX Electronics Corporation

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