AX58200 datasheet(35/180 Pages) ASIX

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AX58200

EtherCAT Slave Controller SoC

System Manager

2.2.1

Overview

System management includes the following sections:

⚫

System Reset

⚫

System Power Distribution

⚫

SRAM Memory Organization

⚫

System Timer (SysTick)

⚫

Nested Vectored Interrupt Controller (NVIC)

⚫

System Control register

2.2.2

System Reset

The system reset can be issued by one of the events listed below. These reset event flags can be read from

SYS_RSTSTS register to determine the reset source. Hardware reset sources are from peripheral signals. Software

reset can trigger reset through setting control registers.

⚫

Hardware Reset Sources

–

Power-on Reset

–

Low level on the nRESET pin

–

Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)

–

Low Voltage Reset (LVR)

–

Brown-out Detector Reset (BOD Reset)

–

CPU Lockup Reset

⚫

Software Reset Sources

–

CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])

–

MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing

1 to SYSRESETREQ (AIRCR[2])

–

CPU Reset for Cortex® -M4 core only by writing 1 to CPURST (SYS_IPRST0[1])

AX58200 Datasheet(PDF) 35 Page - ASIX Electronics Corporation

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