AX58200 datasheet(58/180 Pages) ASIX

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AX58200

EtherCAT Slave Controller SoC

2.3.3

System Clock and SysTick Clock

The system clock has 5 clock sources, which were generated from clock generator block. The clock source switch

depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 2.3-3.

011

010

001

PLLFOUT

LXT

HXT

LIRC

HCLKSEL

(CLK_CLKSEL0[2:0])

HIRC

000

1/(HCLK_N+1)

HCLKDIV

(CLK_CLKDIV0[3:0])

CPU in Power Down Mode

CPU

AHB

APB1

CPUCLK

HCLK

PCLK1

111

1/(HCLK_N+1)

1/(HCLKDIV+1)

APB0

PCLK0

Figure 2.3-3: System Clock Block Diagrams

There are two clock fail detectors to observe HXT and LXT clock source and they have individual enable and

interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically. When LXT detector

is enabled, the LIRC clock is enabled automatically.

When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop being detected

on the following condition: system clock source comes from HXT or system clock source comes from PLL with

HXT as the input of PLL. If HXT clock stop condition is detected, the HXTFIF (CLK_CLKDSTS[0]) is set to 1

and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is set to 1. User can try to recover HXT by disable

HXT and enable HXT again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it

means HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again.

Figure 2.3-4 shows the HXT clock stops detection and system clock switches to HIRC procedure.

AX58200 Datasheet(PDF) 58 Page - ASIX Electronics Corporation

AX58200 Datasheet(HTML) 58 Page - ASIX Electronics Corporation

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