AX58200 datasheet(43/180 Pages) ASIX

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AX58200

EtherCAT Slave Controller SoC

There are several wake-up sources in Idle mode and Power-down mode. Table 2.2-4 lists the available clocks for

each power mode.

Power Mode

Normal Mode

Idle Mode

Power-Down Mode

Definition

CPU is in active state

CPU is in sleep state

CPU is in sleep state and all

clocks stop except LXT and

LIRC. SRAM content retended.

Entry Condition

Chip is in normal mode after

system reset released

CPU executes WFI instruction.

CPU sets sleep mode enable

and power down enable and

executes WFI instruction.

Wake-up Sources

N/A

All interrupts

RTC, WDT, I²C, Timer, UART,

BOD,

GPIO,

EINT,

USCI,

USBD, ACMP and BOD.

Available Clocks

All

All except CPU clock

LXT and LIRC

After Wake-up

N/A

CPU back to normal mode

Table 2.2-4: Power Mode Definition Table

Normal Mode

CPU Clock ON

Power-down Mode

CPU Clock OFF

HXT, HIRC, PCLK OFF

Flash Halt

System reset released

CPU executes WFI

Interrupts occur

Idle Mode

CPU Clock OFF

Flash Halt

1. SLEEPDEEP(SCR[2]) = 1

2. PDEN(CLK_PWRCTL[7]) = 1

3. CPU executes WFI

Wake-up events occur

LXT, LIRC ON

HXT, HIRC, PCLK ON

LXT, LIRC ON

HXT, HIRC, LXT, LIRC, HCLK, PCLK ON

Flash ON

Figure 2.2-7: Power Mode State Machine

AX58200 Datasheet(PDF) 43 Page - ASIX Electronics Corporation

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