AX58200 datasheet(79/180 Pages) ASIX

79 / 180 page

AX58200

EtherCAT Slave Controller SoC

Serial Peripheral Interface (SPI)

2.20.1 Overview

The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex

transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The AX58200

contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data received from a

peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each SPI

controller can be configured as a master or a slave device and supports the PDMA function to access the data

buffer. Each SPI controller also supports I2S mode to connect external audio CODEC.

2.20.2 Features

⚫

SPI Mode

–

Up to four sets of SPI controllers

–

Supports Master or Slave mode operation

–

Master mode up to 100 MHz and Slave mode up to 100 MHz (when chip works at VDD =

2.7~3.6V)

–

Configurable bit length of a transaction word from 8 to 32-bit

–

Provides separate 4-level depth transmit and receive FIFO buffers

–

Supports MSB first or LSB first transfer sequence

–

Supports Byte Reorder function

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Supports Byte or Word Suspend mode

–

Supports PDMA transfer

–

Supports one data channel half-duplex transfer

–

Supports receive-only mode

⚫

I2S Mode

–

Supports Master or Slave

–

Capable of handling 8-, 16-, 24- and 32-bit word sizes

–

Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving

–

Supports monaural and stereo audio data

–

Supports PCM mode A, PCM mode B, I2S and MSB justified data format

–

Supports two PDMA requests, one for transmitting and the other for receiving

QSPIx

SPIx

Dual/Quad I/O Mode

Two-bit Transfer Mode

FIFO Depth

8-level

SPI mode 8~16 bits data length: 8-level

Otherwise: 4-level

Slave Time-out Function

Slave 3-Wired Mode

2S Mode

AX58200 Datasheet(PDF) 79 Page - ASIX Electronics Corporation

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