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AX58200 Datasheet(PDF) 29 Page - ASIX Electronics Corporation |
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AX58200 Datasheet(HTML) 29 Page - ASIX Electronics Corporation |
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29 / 180 page  29 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC Pin No Pin Name Type MFP Description PULAB O5 Pulse AB, toggle when programmable point A and B MDIO B5 PHY Management Interface data H11 IO[18] B5/8m Digital /General Purpose I/O[23:16] LA[10] I5 Local bus Address bus PULC O5 Pulse C, PWM period central point MDC O5 PHY Management Interface clock G11 IO[19] B5/8m Digital /General Purpose I/O[23:16] LA[11] I5 Local bus Address bus PULZ O5 Pulse Z, PWM period start point TXD[0] \ LINK_POL O5 Transmit data [0] These pins are input direction during chip reset use to bootstrap the mode setting to decide external PHY’s LINK polarity, please refer to Section 3.1. H9 IO[20] B5/8m Digital /General Purpose I/O[23:16] LA[12] I5 Local bus Address bus PULB O5 Pulse B, programmable point B TXD[1] TXD[2:1]\ TX_SH[1:0] O5 Transmit data [2:1] This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the external PHY’s TXD phase shift, please refer to Section 2.43.4.1. A9 IO[21] B5/8m Digital /General Purpose I/O[23:16] LA[13] I5 Local bus Address bus PULA O5 Pulse A, programmable point A TXD[2] TXD[2:1]\ TX_SH[1:0] O5 Transmit data [2:1] This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the external PHY’s TXD phase shift, please refer to Section 2.43.4.1. B7 IO[22] B5/8m Digital /General Purpose I/O[23:16] LBHE I5 Local bus Byte High Enable (16-bit width only) PWM3H O5/T PWM 3 High pin TXD[3] O5 Transmit data [3] A7 IO[23] B5/8m Digital /General Purpose I/O[23:16] PWM3L O5/T PWM 3 Low pin TX_EN O5 Transmit enable B6 IO[24] B5/8m Digital/General Purpose I/O[31:24] LDA[8] B5 Local bus Data bus [15:8] PWM2H O5/T PWM 2 High pin RXD[0] I5 Receive data B5 IO[25] B5/8m Digital/General Purpose I/O[31:24] LDA[9] B5 Local bus Data bus [15:8] PWM2L O5/T PWM 2 Low pin RXD[1] I5 Receive data B4 IO[26] B5/8m Digital/General Purpose I/O[31:24] LDA[10] B5 Local bus Data bus [15:8] PWM1H O5/T PWM 1 High pin or DIR pin RXD[2] I5 Receive data H3 IO[27] B5/8m Digital/General Purpose I/O[31:24] LDA[11] B5 Local bus Data bus [15:8] PWM1L O5/T PWM 1 Low pin or STEP pin |
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