DF69 datasheet(40/106 Pages) PADAUK

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DF69

DC Fan Controller

5-10. WatchDog Timer

The watchdog timer (WDT) is a counter with clock coming from ILRC and its frequency is about 24 KHz.

There are four different timeout periods of watchdog timer can be chosen by setting the misc register, it is:

 256 ILRC period when misc[1:0]=11

 16384 ILRC period when misc[1:0]=10

 4096 ILRC period when misc[1:0]=01

 2048 ILRC period when misc[1:0]=00 (default)

The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature;

user should reserve guard band for safe operation. WDT can be cleared by power-on-reset or by command

wdreset at any time. When WDT is timeout, DF69 will be reset to restart the program execution. The relative

timing diagram of watchdog timer is shown as Fig.5-10-1. Please notice that the clock source will be switched

to system clock (for example: 4MHz) when fast wakeup is enabled, therefore, it is recommended to turn off

the watchdog timer before enabling the fast wakeup and turn on the watchdog timer after disabling the fast

wakeup.

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

Fig. 5-10-1 Time-Out Sequence of WatchDog Timer

Page 40 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 40 Page - PADAUK Technology.