DF69 datasheet(32/106 Pages) PADAUK

32 / 106 page

DF69

DC Fan Controller

5-7-3 IHRC Frequency Calibration and System Clock

During compiling the user program, the options for IHRC calibration and system clock are shown as Table 4:

SYSCLK

CLKMD

IHRCR

Description

○ Set IHRC / 2

= 34h (IHRC / 2)

Calibrated

IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)

○ Set IHRC / 4

= 14h (IHRC / 4)

Calibrated

IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)

○ Set IHRC / 8

= 3Ch (IHRC / 8)

Calibrated

IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)

○ Set IHRC / 16

= 1Ch (IHRC / 16)

Calibrated

IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)

○ Set IHRC / 32

= 7Ch (IHRC / 32)

Calibrated

IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)

○ Set ILRC

= E4h (ILRC / 1)

Calibrated

IHRC calibrated to 16MHz, CLK=ILRC

○ Disable

No change

No Change

IHRC not calibrated, CLK not changed

Table 4 Options for IHRC Frequency Calibration

Usually, .ADJUST_IC will be the first

command after boot up, in order to set the target operating frequency

whenever stating the system. The program code for IHRC frequency calibration is executed only one time that

occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for

IHRC calibration is chosen, the system status is also different after boot. The following shows the status of

DF69 for different option:

(1) .ADJUST_IC

SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V, Band-gap =On

After boot up, CLKMD = 0x34：

 IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled

 System CLK = IHRC/2 = 8MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(2) .ADJUST_IC

SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V, Band-gap =On

After boot, CLKMD = 0x14：

 IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled

 System CLK = IHRC/4 = 4MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(3) .ADJUST_IC

SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V, Band-gap =On

After boot, CLKMD = 0x3C：

 IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled

 System CLK = IHRC/8 = 2MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

(4) .ADJUST_IC

SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.2V, Band-gap =On

After boot, CLKMD = 0x1C：

 IHRC frequency is calibrated to 16MHz@VDD=2.2V and IHRC module is enabled

 System CLK = IHRC/16 = 1MHz

 Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V

Page 32 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 32 Page - PADAUK Technology.

DF69 Datasheet(HTML) 32 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL