DF69 datasheet(77/106 Pages) PADAUK

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DF69

DC Fan Controller

6-40 Pulse Capture Control Register (plscc), IO address = 0x34

Bit

Reset

R/W

Description

R/W

Start to do Pulse Capture.

After writing this bit “1”. It starts the Pulse Capture operation and clears this bit

automatically after finishing the Pulse Capture operation

R/W

Pulse Capture overflow. This bit is set to “1” when the Pulse Capture counter overflows.

R/W

Pulse Capture front edge selection.

0: rising edge; 1:falling edge.

R/W

Pulse Capture back edge selection.

0: rising edge; 1:falling edge.

Reserved.

2 – 0

000

R/W

Sources for Pulse Capture.

000: PA0

001: PA5

010: PA6

011: PB0

100: PB7

101: comparator output

Others: reserved.

6-41 Pulse Capture Scalar Register (plscs), IO address = 0x35

Bit

Reset

R/W

Description

7 – 4

Reserved.

3 – 2

Pulse Capture clock source.

00: system clock

01: IHRC

10: EOSC (external oscillator clock)

1 – 0

Pulse Capture clock divider.

00 : /1

01 : /4

10 : /16

11 : /64

6-42 Pulse Capture Result High Register (plsrh), IO address = 0x36

Bit

Reset

R/W

Description

7 – 0

Pulse Capture result high.

Page 77 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 77 Page - PADAUK Technology.

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