DF69 datasheet(75/106 Pages) PADAUK

75 / 106 page

DF69

DC Fan Controller

6-32. Hall Comparator 1 Adjust Register (HC1A), IO address = 0x2b

Bit

Reset

R/W

Description

R/W

Hall comparator positive pin selection.

0: PA4

1: 1.2V Band-gap

6 – 5

R/W

Hall comparator negative pin selection.

00: PA0

01: PA1

10: PA2

11: 1.2V Band-gap

4 – 0

5’h00

R/W

Hall comparator 1 (HC_1) adjust bits.

6-33. Hall Comparator 2 Adjust Register (HC2A), IO address = 0x2c

Bit

Reset

R/W

Description

7 – 5

3’h00

R/W

Reversed

4 – 0

5’h00

R/W

Hall comparator 2 (HC_2) adjust bits.

6-34 PWM Generator control Register (pwmc), IO address = 0x30

Bit

Reset

R/W

Description

R/W

Enable PWM generator. 0 / 1 : disable / enable.

Output of PWM generator.

R/W

Enable to inverse the polarity of PWM generator output. 0 / 1 : disable / enable.

R/W

PWM counter reset.

Writing “1” to clear PWM counter and this bit will be self clear to 0 after counter reset.

3 – 1

R/W

Select PWM output pin.

000: disable

010: PA6

011: PA7

100: PA2

101: PA3

110: PA4

Others: reserved

R/W

Clock source of PWM generator. 0: system clock , 1: IHRC

Page 75 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 75 Page - PADAUK Technology.

DF69 Datasheet(HTML) 75 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL