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DF69

DC Fan Controller

5-12-2. Power-Down mode (“stopsys”)

Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using

the “stopsys” instruction, this chip will be put on Power-Down mode directly. The internal low frequency RC

oscillator must be enabled before entering the Power-Down mode, means that bit 2 of register clkmd (0x03)

must be set to high before issuing “stopsys” command in order to resume the system when wakeup. The

following shows the internal status of DF69 in detail when “stopsys” command is issued:

 All the oscillator modules are turned off

 Enable internal low RC oscillator (set bit 2 of register clkmd)

 OTP memory is turned off

 The contents of SRAM and registers remain unchanged

 Wake-up sources: ANY IO toggle.

 If PA or PB is input mode and set to analog input by padier or pbdier register, it can NOT be used to

Wake-up the system.

Wake-up from input pins can be considered as a continuation of normal execution. To minimize power

consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The

reference sample program for power down is shown as below:

CMKMD

0xF4;

Change clock from IHRC to ILRC

CLKMD.4

disable IHRC

…

while (1)

{

STOPSYS;

enter power-down

(…)

break;

if wakeup happen and check OK, then return to high speed,

else stay in power-down mode again.

}

CLKMD

0x34;

Change clock from ILRC to IHRC/2

Page 44 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 44 Page - PADAUK Technology.