DF69 datasheet(31/106 Pages) PADAUK

31 / 106 page

DF69

DC Fan Controller

5-6. Arithmetic and Logic Unit

Arithmetic and Logic Unit (ALU) is the computation element to operate integer arithmetic, logic, shift and other

specialized operations. The operation data can be from instruction, accumulator or SRAM data memory.

Computation result could be written into accumulator or SRAM. All the FPP units share the ALU for its

corresponding operation.

5-7. Oscillator and clock

There are three oscillator circuits provided by DF69: external crystal oscillator (EOSC), internal high RC

oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or disabled by

registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three oscillators as

system clock source and use clkmd register to target the desired frequency as system clock to meet different

application.

Oscillator Module

Enable/Disable

Default after boot-up

EOSC

eoscr.7

Disabled

IHRC

clkmd.4

Enabled

ILRC

clkmd.2

Enabled

5-7-1. Internal High RC oscillator and Internal Low RC oscillator

After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to

eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. The frequency deviation can

be within 1% normally after calibration and it still drifts slightly with supply voltage and operating temperature,

the total drift rate is about ±4% for VDD=3.5V~5.5V and -40

oC~85oC operating conditions. Please refer to

the measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature.

The frequency of ILRC is around 24 KHz, however, its frequency will vary by process, supply voltage and

temperature, please refer to DC specification and do not use for accurate timing application.

5-7-2. Chip calibration

The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing

variation, DF69 provide both the IHRC frequency calibration and band-gap calibration to eliminate this

variation, and this function can be selected when compiling user’s program and the command will be

inserted into user’s program automatically. The calibration command is shown as below:

.ADJUST_IC

SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V, Band-gap=(p4);

Where,

p1=2, 4, 8, 16, 32; In order to provide different system clock.

p2=16 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.

p3=2.2 ~ 5.5; In order to calibrate the chip under different supply voltage.

p4= On or Off; Band-gap calibration is On or Off.

Page 31 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 31 Page - PADAUK Technology.

DF69 Datasheet(HTML) 31 Page - PADAUK Technology.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL