DF69 datasheet(29/106 Pages) PADAUK

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DF69

DC Fan Controller

5-4. Boot Procedure

POR (Power-On-Reset) is used to reset DF69 when power up, however, the supply voltage may be not stable.

To ensure the stability of supply voltage after power up, it will wait 1024 ILRC clock cycles before first

instruction being executed, which is tSBP and shown in the Fig. 5-4-1. After boot up procedure, the default

system clock is ILRC. If user wants to switch the system clock source from ILRC to IHRC or EOSC, user must

enable the corresponding oscillator module and make sure clock is already stable.

VDD

POR

Program

Execution

tSBP

Boot up from Power-On Reset

Fig. 5-4-1 Power-On Sequence

Fig. 5-4-2 shows the typical program flow after boot up, it shows all the FPP units are used. Please notice that

the FPP1~FPP7 are disabled after reset, recommending NOT to enable FPP1~FPP7 before system and FPP0

initialization.

Fig. 5-4-2 Boot Procedure

Start

Set the Stack of FPP1

FPP0

Initialize the system clock

Initialize the IO

Initialize the shared resources

Set the stack of FPP0

Enable FPP1

Enable FPP2

FPP0 Firmware

FPP1 Firmware

Set the Stack of FPP2

Enable FPP3

FPP2 Firmware

Set the Stack of FPP7

FPP7 Firmware

Set the Stack of FPP6

Enable FPP7

FPP6 Firmware

。。。

Page 29 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 29 Page - PADAUK Technology.