DF69 datasheet(72/106 Pages) PADAUK

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DF69

DC Fan Controller

6-23. ADC Control Register (adcc), IO address = 0x20

Bit

Reset

R/W

Description

R/W

Enable ADC function. 0/1: Disable/Enable.

R/W

ADC process control bit.

Write “1” to start AD conversion, and the flag is cleared automatically when starting the

AD conversion ;

Read “1” to indicate the completion of AD conversion and “0” is in progressing.

5 – 2

0000

R/W

Channel selector. These four bits are used to select input signal for AD conversion.

0000: PB0/AD0,

0001: PB1/AD1,

0010: PB2/AD2,

0011: PB3/AD3,

0100: PB4/AD4,

0101: PB5/AD5,

0110: PB6/AD6,

0111: PB7/AD7

1000: PA3/AD8

1001: PA4/AD9

1111: Band-gap 1.20 volt reference voltage

Others: reserved

1 - 0

Reserved. Please keep 0.

6-24. ADC Mode Register (adcm), IO address = 0x21

Bit

Reset

R/W

Description

7 – 5

000

Bit Resolution of ADC.

000: 8-bit, AD 8-bit result [7:0] = adcrh[7:0].

001: 9-bit, AD 9-bit result [8:0] = { adcrh[7:0], adcrl[7] }.

010: 10-bit, AD 10-bit result [9:0] = { adcrh[7:0], adcrl[7:6] }.

others: reserved,

4 – 1

000

ADC clock source selection.

0000: sysclk/1,

0001: sysclk/2,

0010: sysclk/4,

0011: sysclk/8,

0100: sysclk/16,

0101: sysclk/32,

0110: sysclk/64,

0111: sysclk/128,

Others: reserved.

Reserved

Page 72 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

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