DF69 datasheet(47/106 Pages) PADAUK

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DF69

DC Fan Controller

Other than PA5, all the IO pins have the same structure; PA5 can is open-drain ONLY when setting to output

mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent

leakage current for those pins are selected to be analog function. When DF69 is put in power-down or

power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins

needed to wake-up system must be set to input mode and set the corresponding bits of registers padier and

pbdier to high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin and

pbdier.0 for PB0.

5-14. Reset and LVD (Low Voltage Detection)

5-14-1. Reset

There are many causes to reset the DF69, once reset is asserted, most of all the registers in DF69 will be

set to default values, When reset comes from WDT timeout, gdio register (IO address 0x7) keeps the same

value, system should be restarted once abnormal cases happen, or by jumping program counter to

address ’h0. The data memory is in uncertain state when reset comes from power-up and LVD; however,

the content will be kept when reset comes from PRST# pin or WDT timeout.

5-14-2. LVD reset

By code option, there are 8 different levels of LVD for reset ~ 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V and

1.8V; usually, user selects LVD reset level to be in conjunction with operating frequency and supply voltage.

Page 47 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

DF69 Datasheet(PDF) 47 Page - PADAUK Technology.