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DF69 Datasheet(PDF) 53 Page - PADAUK Technology. |
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DF69 Datasheet(HTML) 53 Page - PADAUK Technology. |
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53 / 106 page  DF69 DC Fan Controller 5-17 10-BIT PWM generator 5-17-1. PWM Waveform A PWM output waveform (Fig. 5-17-1) has a time-base (TPeriod = Time of Period) and a time with output high level (Duty Cycle). The frequency of the PWM output is the inverse of the period (fPWM = 1/TPeriod), the resolution of the PWM is the clock count numbers for one period (N bits resolution, 2 N × T clock = TPeriod). Fig. 5-17-1 PWM Output Waveform 5-17-2. Hardware and Timing Diagram One 10-bit hardware PWM generator is built inside the DF69; Fig. 5-17-2 shows its hardware diagram. The clock source can be IHRC or system clock and output pin can be PA2, PA3, PA4, PA6 or PA7 via pwmc register selection. The period of PWM waveform is defined in the PWM upper bond high and low registers, the dut y c yc le of PW M wavef orm is def ine d in the PW M dut y high and lo w regist ers. Fig. 5-17-2 Hardware Diagram of 10-bit PWM Generator Period Duty Cycle ‧‧‧‧‧‧‧ clock N bit resolution M U X pwmc.0 Pre- scalar ÷ 1, 4, 16, 64 pwms[6:5] Scalar ÷ 1 ~ 31 pwms[4:0] 10-bit PWM down-counter X O R S E L E C T O R pwmc[3:1] pwmc.5 IHRC clock CLK System clock PA6 PA7 PA3 PA4 PWM reset pwmc.1 PWM enable pwms.7 Duty Value (High) Duty Value (Low) Duty Value Low Buffer 8 bits 2 bits wr_pwmdth wr_pwmdtl Duty Value Buffer (10 bits) PWM counter upper bond (high) 8 bits 2 bits wr_pwmcubh wr_pwmcubl upper-bound (10 bits) PWM counter upper bond (low) Equal ? reload reload compare & Output control PWM interrupt selection PWM interrupt mode pwms.7 PWM interrupt request 10-bit or 11-bit M U X pwmc.0 Pre- scalar ÷ 1, 4, 16, 64 pwms[6:5] Scalar ÷ 1 ~ 31 pwms[4:0] 10-bit PWM down-counter X O R S E L E C T O R pwmc[3:1] pwmc.5 IHRC clock CLK System clock PA6 PA7 PA3 PA4 PWM reset pwmc.1 PWM enable pwms.7 Duty Value (High) Duty Value (Low) Duty Value Low Buffer 8 bits 2 bits wr_pwmdth wr_pwmdtl Duty Value Buffer (10 bits) PWM counter upper bond (high) 8 bits 2 bits wr_pwmcubh wr_pwmcubl upper-bound (10 bits) PWM counter upper bond (low) Equal ? reload reload compare & Output control PWM interrupt selection PWM interrupt mode pwms.7 PWM interrupt request 10-bit or 11-bit ©Copyright 2018, PADAUK Technology Co. Ltd Page 53 of 106 PDK-DS-DF69_V003 – Apr. 18, 2018 |
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