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DF69 Datasheet(PDF) 22 Page - PADAUK Technology. |
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DF69 Datasheet(HTML) 22 Page - PADAUK Technology. |
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22 / 106 page  DF69 DC Fan Controller Fig. 5-1-2 shows the timing sequence of FPP units for pmode=0 which will assign the bandwidth to two FPP units only. FPP0 and FPP1 each have half computing power of whole system; for pmode=0, FPP0 and FPP1will be operated at 4MHz if system clock is 8MHz. For FPP0 unit, its program will be executed in sequence every other system clock, shown as (M-1)th, Mth, …. (M+4)th instructions. For FPP1 unit, its program will be also executed in sequence every other system clock, shown as (N-1)th, Nth, …. (N+3)th instructions. Fig. 5-1-2 Timing Sequence of Processing units for pmode=0 System Clock Time FPP0 active FPP1 active Mth (M+1)th (M-1)th Nth (N+1)th (N-1)th (M+2)th (M+3)th (M+4)th (N+2)th (N+3)th PMODE=0 (FPP0 and FPP1 are active, FPP2~FPP7 are inactive) ©Copyright 2018, PADAUK Technology Co. Ltd Page 22 of 106 PDK-DS-DF69_V003 – Apr. 18, 2018 |
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