DF69 datasheet(14/106 Pages) PADAUK

14 / 106 page

DF69

DC Fan Controller

Symbol

Description

Min

Typ

Max

Unit

Conditions (Ta=25

℃)

tWUP

System wake-up period

Fast wake-up by IO toggle from

STOPEXE suspend

128

TSYS

Where TSYS is the time

period of system clock

Fast wake-up by IO toggle from

STOPSYS suspend, IHRC is the

system clock

128

TSYS

TSIHRC

Where TSIHRC is the stable time

of IHRC from power-on.

Fast wake-up by IO toggle from

STOPSYS suspend, ILRC is the

system clock

128

TSYS

TSILRC

Where TSILRC is the stable time

of ILRC from power-on.

Normal wake-up from STOPEXE or

STOPSYS suspend

1024

TILRC

Where TILRC is the clock

period of ILRC

HCPos

Comparator offset*

±10

±20

HCPcm

Comparator input common mode*

VDD-1.

HCPspt

Comparator response time**

100

500

Both Rising and Falling

HCPmc

Stable time to change comparator

mode

2.5

7.5

*These parameters are for design reference, not tested for each chip.

The larger fIHRC drift will have adverse effect on the RPM accuracy for DF69 DC Fan application.

** Response time is measured with comparator input at (VDD-1.5)/2 -100mV, and (VDD-1.5)/2+100mV.

Page 14 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

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