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DF69 Datasheet(PDF) 33 Page - PADAUK Technology. |
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DF69 Datasheet(HTML) 33 Page - PADAUK Technology. |
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33 / 106 page  DF69 DC Fan Controller (5) .ADJUST_IC SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V, Band-gap =Off After boot, CLKMD = 0x7C： IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled System CLK = IHRC/32 = 500KHz Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode (6) .ADJUST_IC SYSCLK=ILRC, IHRC=16MHz, VDD=5V, Band-gap =Off After boot, CLKMD = 0XE4： IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled System CLK = ILRC Watchdog timer is enabled, ILRC is enabled, PA5 is input mode (7) .ADJUST_IC DISABLE After boot, CLKMD is not changed (Do nothing)： IHRC is not calibrated and IHRC module is disabled System CLK = ILRC Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode ©Copyright 2018, PADAUK Technology Co. Ltd Page 33 of 106 PDK-DS-DF69_V003 – Apr. 18, 2018 |
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