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DF69 Datasheet(PDF) 36 Page - PADAUK Technology.

Part # DF69
Description  DC Fan Controller
PDF  106 Pages
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Manufacturer  PADAUK [PADAUK Technology.]
Direct Link  http://www.padauk.com.tw/
Logo PADAUK - PADAUK Technology.

DF69 Datasheet(HTML) 36 Page - PADAUK Technology.

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DF69
DC Fan Controller
5-7-5. System Clock and LVR (Low Voltage Reset) level
The system clock of DF69 can come from EOSC, IHRC or ILRC, the hardware diagram for system clock in
the DF69 is shown as Fig. 5-7-2. DF69 can provide the wide range system clock via clkmd register selection.
After power up, the running system clock will be ILRC/1, user can change the system clock any time by
setting clkmd register and the new system clock will be changed into the new one immediately after writing
the clkmd register.
Fig. 5-7-2 Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be in conjunction with supply voltage and LVR level to ensure system stable. The LVR level can
be selected during compilation, the following operating frequency and LVR level is recommended:
 system clock = 8MHz with LVR=3.5V
 system clock = 4MHz with LVR=2.5V
 system clock = 2MHz with LVR=2.2V
M
U
X
clkmd[7:5]
System
clock
CLK
÷2, ÷4, ÷8,
÷16, ÷32, ÷64
÷1, ÷2, ÷4, ÷8
÷1 (default), ÷4
IHRC
clock
ILRC
clock
EOSC
clock
M
U
X
clkmd[7:5]
System
clock
CLK
÷2, ÷4, ÷8,
÷16, ÷32, ÷64
÷1, ÷2, ÷4, ÷8
÷1 (default), ÷4
IHRC
clock
ILRC
clock
EOSC
clock
©Copyright 2018, PADAUK Technology Co. Ltd
Page 36 of 106
PDK-DS-DF69_V003 – Apr. 18, 2018



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