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DF69 Datasheet(PDF) 105 Page - PADAUK Technology. |
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DF69 Datasheet(HTML) 105 Page - PADAUK Technology. |
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105 / 106 page ![]() DF69 DC Fan Controller 9. POR for DC Fan Application As shown in Fig 9-1, DF69 generates a good power on reset (POR) signal when VDD rises from 0V to 5V in TPOR (max. 50ms) and rises through the voltage range of 0.7V to 1.6V in TFSV (max. 10ms). If there are a lot of abnormal power noises in VDD power-on time period and TPOR and TFSV do not meet the specifications, DF69 is not able to guarantee circuit initialization and may cause a malfunction. 5V VDD VDD Power-on Time 0V 0.7V 1.6V TFSV TPOR TFSV < 10ms TPOR < 50ms time Fig. 9-1 During power-off as shown in Fig 9-2 and Fig 9-3, VDD has to be discharged to VPDRV (max. is 0.7V) for the next power-on. In case VDD is more than VPDRV, it is not recognized to do the next power-on. 5V VDD Power-off 0V Max. is 0.7V time VDD VPDRV 5V VDD Power-off 0V Max. is 0.7V time VDD VPDRV Fig. 9-2 Fig. 9-3 NOTICE: It may cause DF69 malfunction, fail or crash when power-on and power-off do not meet the specifications. Another proper POR is needed in order to get rid of such status. ©Copyright 2018, PADAUK Technology Co. Ltd Page 105 of 106 PDK-DS-DF69_V003 – Apr. 18, 2018 |
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