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AD9082

Data Sheet

Rev. A | Page 6 of 33

POWER CONSUMPTION

Typical at nominal supplies and maximum at 5% supplies. DAC datapath with a complex I/Q data rate frequency (fIQ_DATA) = 375 MSPS and

DAC frequency (fDAC) of 12 GSPS with interpolate by 32× with JRx mode of 16B (L = 8, M = 16). ADC datapath with fIQ_DATA = 375 MSPS and

fADC of 6 GSPS with decimate by 16× with JTx mode of 17B (L = 8, M = 16). For the minimum and maximum values, TJ = −40°C to +120°C.

For the typical values, TA = 25°C, unless otherwise noted.

See the UG-1578 user guide for further information on the JESDB or JESDC mode configurations and detailed settings referred to

throughout this data sheet.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CURRENTS

AVDD2 (IAVDD2)

2.0 V supply

190

BVDD2 (IBVDD2) + RVDD2 (IRVDD2)

2.0 V supply

292

AVDD2_PLL (IAVDD2__PLL) + SVDD2_PLL (ISVDD2__PLL)

2.0 V supply

Power Dissipation for 2 V Supplies

2.0 V supply total power dissipation

1.05

PLLCLKVDD1 (IPLLCLKVDD1)

1.0 V supply

AVDD1 (IAVDD1) + DCLKVDD1(IDCLKVDD1)

1.0 V supply

1541

AVDD1_ADC (IAVDD1_ADC)

1.0 V supply

1700

CLKVDD1 (ICLKVDD1)

1.0 V supply

FVDD1 (IFVDD1)

1.0 V supply

72.5

VDD1_NVG (IVDD1_NVG)

1.0 V supply

290

DAVDD1 (IDAVDD1)

1.0 V supply

985

DVDD1 (IDVDD1)

1.0 V supply

3555

DVDD1_RT (IDVDD1_RT)

1.0 V supply

461

SVDD1 (ISVDD1) + SVDD1_PLL (ISVDD1_PLL)

1.0 V supply

1626

Power Dissipation for 1 V Supplies

1.0 V supply total power dissipation

10.4

DVDD1P8 (IDVDD1P8)

1.8 V supply

6.8

Total Power Dissipation

Total power dissipation of 2 and 1 V supplies

11.45

CLOCK INPUT AND PHASE-LOCKED LOOP (PLL) FREQUENCY SPECIFICATIONS

For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

PLL VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY RANGES

VCO Output

Divide by 1

GSPS

Divide by 2

GSPS

Divide by 4

1.5

GSPS

PHASE FREQUENCY DETECT INPUT FREQUENCY RANGES

750

MHz

CLOCK INPUTS (CLKINP, CLKINN) FREQUENCY RANGES

PLL Off

1.45

GHz

PLL On

M divider set to divide by 1

750

MHz

M divider set to divide by 2

1500

MHz

M divider set to divide by 3

2250

MHz

M divider set to divide by 4

100

3000

MHz

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