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AD9082 Datasheet(PDF) 19 Page - Analog Devices |
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AD9082 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 33 page  Data Sheet AD9082 Rev. A | Page 19 of 33 Pin No. Mnemonic Type Description D12, D11 ADC0_SMON0, ADC0_SMON1 Output ADC0 Signal Monitoring Outputs by Default. Do not connect if unused. E12, E11 ADC1_SMON0, ADC1_SMON1 Output ADC1 Signal Monitoring Outputs by Default. Do not connect if unused. F12, F11 ADC0_FD0, ADC0_FD1 Output ADC0 Fast Detect Outputs by Default. Do not connect if unused. G12, G11 ADC1_FD0, ADC1_FD1 Output ADC1 Fast Detect Outputs by Default. Do not connect if unused. P12, R12 IRQB_0, IRQB_1 Outputs Interrupt Request 0 and 1 Outputs. These pins are an open-drain, active low output (CMOS levels with respect to DVDD1P8). Connect a 10 kΩ pull-up resistor to DVDD1P8 to prevent these pins from floating when unused. K13, L13, M11 to M13, N11 to N13, P11, R11, T12 GPIO0 to GPIO10 Input/output General-Purpose Input or Output Pins. JESD204B or JESD204C COMPATIBLE SERDES DATA LANES AND CONTROL SIGNALS2 L18, L17 SERDIN0+, SERDIN0− Input JRx Lane 0 Inputs, Data True/Complement. N18, N17 SERDIN1+, SERDIN1− Input JRx Lane 1 Inputs, Data True/Complement. R18, R17 SERDIN2+, SERDIN2− Input JRx Lane 2 Inputs, Data True/Complement. U18, U17 SERDIN3+, SERDIN3− Input JRx Lane 3 Inputs, Data True/Complement. M15, M14 SERDIN4+, SERDIN4− Input JRx Lane 4 Inputs, Data True/Complement. V15, V14 SERDIN5+, SERDIN5− Input JRx Lane 5 Inputs, Data True/Complement. T15, T14 SERDIN6+, SERDIN6− Input JRx Lane 6 Inputs, Data True/Complement. P15, P14 SERDIN7+, SERDIN7− Input JRx Lane 7 Inputs, Data True/Complement. U13, V13 SYNC0OUTB+, SYNC0OUTB− Output JRx Link 0 Synchronization Outputs for JESD204B interface. These pins are LVDS or CMOS configurable. These pins can also provide differential 100 Ω output impedance in LVDS mode. U12, V12 SYNC1OUTB+, SYNC1OUTB− Output JRx Link 1 Synchronization Outputs for JESD204B interface or CMOS Input for Transmit Fast Frequency Hopping (FFH) via GPIOx pins. For sync output function, these pins are LVDS or CMOS output configurable and can provide differential 100 Ω output impedance in LVDS mode. A15, A14 SERDOUT0+, SERDOUT0− Output JTx Lane 0 Outputs, Data True/Complement. C15, C14 SERDOUT1+, SERDOUT1− Output JTx Lane 1 Outputs, Data True/Complement. E15, E14 SERDOUT2+, SERDOUT2− Output JTx Lane 2 Outputs, Data True/Complement. G15, G14 SERDOUT3+, SERDOUT3− Output JTx Lane 3 Outputs, Data True/Complement. H18, H17 SERDOUT4+, SERDOUT4− Output JTx Lane 4 Outputs, Data True/Complement. |
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