AD9082 datasheet(18/33 Pages) AD

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AD9082

Data Sheet

Rev. A | Page 18 of 33

Pin No.

Mnemonic

Type

Description

ANALOG OUTPUTS

B1, C1

DAC0P, DAC0N

Output

DAC0 Output Currents, Ground Referenced.

G1, F1

DAC1P, DAC1N

Output

DAC1 Output Currents, Ground Referenced.

M1, N1

DAC2P, DAC2N

Output

DAC2 Output Currents, Ground Referenced.

U1, T1

DAC3P, DAC3N

Output

DAC3 Output Currents, Ground Referenced.

ISET

Output

DAC Bias Current Setting Pin. Connect this pin

with a 5 kΩ resistor to GND.

C4, C3

ADCDRVP,

ADCDRVN

Output

ADC Clock Output Options. These pins are

disabled by default.

B8, U8

VCM0, VCM1

Output

ADC Buffer Common-Mode Output Voltage.

Decouple this pin to GND with a 0.1 μF capacitor.

VCO_VREG

Output

PLL LDO Regulator Output. Decouple this pin to

GND with a 2.2 μF capacitor.

TMU_REFN

Output

TMU ADC Negative Reference. Connect this pin

to GND.

G10

TMU_REFP

Output

TMU ADC Positive Reference. Connect this pin

to DVDD1P8.

ANALOG INPUTS

A10, A9

ADC0P, ADC0N

Input

ADC0 Differential Inputs with Internal 100 Ω

Differential Resistor.

V10, V9

ADC1P, ADC1N

Input

ADC1 Differential Inputs with Internal 100 Ω

Differential Resistor.

VCO_FINE

Input

On-Chip Clock Multiplier and PLL Fine Loop

Filter Input.

VCO_COARSE

Input

On-Chip DAC Clock Multiplier and PLL Coarse

Loop Filter Input.

VCO_VCM

Input

On-Chip Clock Multiplier and VCO Common-

Mode Input.

N9, N10

TDP, TDN

Input

Anode and Cathode of Temperature Diodes.

This feature is not supported. Tie TDP and TDN

to GND.

J1, K1

CLKINP, CLKINN

Input

Differential Clock Inputs with Nominal 100 Ω

Termination. Self bias input requiring ac

coupling. When the on-chip clock multiplier PLL

is enabled, this input is the reference clock

input. If the PLL is disabled, an RF clock equal to

the DAC output sample rate is required.

CMOS INPUTS AND OUTPUTS1

G13

CSB

Input

Serial Port Enable Input. Active low.

H13

SCLK

Input

Serial Plot Clock Input.

F13

SDIO

Input/output

Serial Port Bidirectional Data Input/Output.

J13

SDO

Output

Serial Port Data Output.

C12

RESETB

Input

Active Low Reset Input. RESETB places digital

logic and SPI registers in a known default state.

RESETB must be connected to a digital IC that is

capable of issuing a reset signal for the first step

in the device initialization process.

E13, D13

RXEN0, RXEN1

Input

Active High ADC and Receive Datapath Enable

Inputs. RXENx is also SPI configurable.

P13, R13

TXEN0, TXEN1

Input

Active High DAC and Transmit Datapath Enable

Inputs. TXENx is also SPI configurable.

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