AD9082

Data Sheet

Rev. A | Page 8 of 33

JESD204B AND JESD204C INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS

Table 7.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

JESD204B SERIAL INTERFACE RATE

Serial lane rate (bit repeat option disabled)

8.11

15.5

Gbps

Unit Interval

168.35

64.5

ps

JESD204C SERIAL INTERFACE RATE

Serial lane rate (bit repeat option disabled)

8.11

16.22

Gbps

Unit Interval

123.3

61.65

ps

JESD204x DATA INPUTS

SERDINx±, where x = 0 to 7

800

mV p-p

At dc

98

Ω

AC-coupled

0.97

V

JESD204x DATA OUTPUTS

SERDOUTx±, where x = 0 to 7

Logic Compliance

JESD204B/JESD204C compliant

Differential Output Voltage

Maximum strength

675

mV p-p

Differential Termination Impedance

80

108

120

Ω

20% to 80% into 100 Ω load

18

ps

20% to 80% into 100 Ω load

18

ps

SYSREFP AND SYSREFN INPUTS

Logic Compliance

Differential Input Voltage

0.7

1.9

V p-p

Input Common-Mode Voltage Range

DC-coupled

0.675

2

V

100

Ω

Input Capacitance (Differential)

1

pF

Where x = 0 or1

Driving 100 Ω differential load

400

mV

DVDD1P8/2

V

SYNCxOUTB+

CMOS output option

Refer to CMOS pin specification

Where x = 0 or1

Logic Compliance

LVDS

Differential Input Voltage

0.7

1.9

mV p-p

Input Common-Mode Voltage

DC-coupled

0.675

2

V

18

18

kΩ

Input Capacitance (Differential)

1

1

pF

SYNCxINB+ INPUT

CMOS input option

Refer to CMOS pin specification

1

LVDS means low voltage differential signaling and LVPECL means low voltage positive/pseudo emitter-coupled logic.

2

IEEE 1596.3 Standard LVDS compatible.