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AD9082 Datasheet(PDF) 1 Page - Analog Devices |
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AD9082 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 33 page ![]() MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Data Sheet AD9082 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) Supports single, dual, and quad band Maximum DAC/ADC sample rate up to 12 GSPS/6 GSPS DAC to ADC sample rate ratios of 1, 2, 3, and 4 ADC and DAC datapath bypass option Analog bandwidth to 8 GHz Full-scale output current range, ac coupling: 7 mA to 40 mA On-chip PLL with multichip synchronization External RFCLK input option ADC ac performance at 6 GSPS Full-scale input voltage: 1.475 V p-p Full-scale sine wave input power: 4.4 dBm Noise density: −153 dBFS/Hz Noise figure: 25.3 dB HD2: −65.2 dBFS at 2.7 GHz HD3: −70.8 dBFS at 2.7 GHz Worst other (excluding HD2 and HD3): −68.5 dBFS at 2.7 GHz DAC ac performance at 3.7 GHz output 2-tone IMD3 (−7 dBFS per tone): −78.9 dBc NSD, single-tone, fDAC = 12 GSPS: −155.1 dBc/Hz SFDR, single-tone, fDAC = 12 GSPS: −70 dBc Versatile digital features Supports real or complex digital data (8-, 12-, 16-, or 24-bit) Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC/DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency digital loopback mode (ADC to DAC) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIOx pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 16.22 Gbps 8 lanes per DACs and ADCs JESD204B compatible with the maximum 15.5 Gbps lane rate JESD204C compatible with the maximum 16.22 Gbps lane rate Sample and bit repeat mode for lane rate matching Total power consumption: 11.45 W typical 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch APPLICATIONS Wireless communications infrastructure Microwave point-to-point, E-band and 5G mmWave Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Phased array radar and electronic warfare Electronic test and measurement systems GENERAL DESCRIPTION The mixed signal front-end (MxFE®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS rate, RF analog-to- digital converter (ADC) core. The AD9082 supports four transmitter channels and two receiver channels. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The device features a 16 lane, 16.22 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port, an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications. The AD9082 also features a bypass mode that allows the full bandwidth capability of the ADC and/or DAC cores to bypass the DSP datapaths. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. |
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