SC3200 datasheet(273/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

273

Core Logic Module - IDE Controller Registers - Function 2

Revision 5.1

6.4.3

IDE Controller Registers - Function 2

The register space designated as Function 2 (F2) is used

to configure Channels 0 and 1 and the PCI portion of sup-

port hardware for the IDE controllers. The bit formats for

the PCI Header/Channels 0 and 1 Registers are given in

Table 6-35.

Located in the PCI Header Registers of F2 is a Base

Address Register (F2BAR4) used for pointing to the regis-

ter space designated for support of the IDE controllers,

described later in this section.

Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value: 100Bh

Index 02h-03h

Device Identification Register (RO)

Reset Value: 0502h

Index 04h-05h

PCI Command Register (R/W)

Reset Value: 0000h

15:3

Reserved. (Read Only)

Bus Master. Allow the Core Logic module bus mastering capabilities.

0: Disable.

1: Enable. (Default)

This bit must be set to 1.

Reserved. (Read Only)

I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.

0: Disable.

1: Enable.

This bit must be enabled, in order to access I/O offsets through F2BAR4 (for more information see F2 Index 20h).

Index 06h-07h

PCI Status Register (RO)

Reset Value: 0280h

Index 08h

Device Revision ID Register (RO)

Reset Value: 01h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value: 010180h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value: 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value: 00h

Index 0Eh

PCI Header Type (RO)

Reset Value: 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value: 00h

Index 10h-13h

Base Address Register 0 - F2BAR0 (RO)

Reset Value: 00000000h

Reserved. Reserved for possible future use by the Core Logic module.

Index 14h-17h

Base Address Register 1 - F2BAR1 (RO)

Reset Value: 00000000h

Reserved. Reserved for possible future use by the Core Logic module.

Index 18h-1Bh

Base Address Register 2 - F2BAR2 (RO)

Reset Value: 00000000h

Reserved. Reserved for possible future use by the Core Logic module.

Index 1Ch-1Fh

Base Address Register 3 - F2BAR3 (RO)

Reset Value: 00000000h

Reserved. Reserved for possible future use by the Core Logic module.

Index 20h-23h

Base Address Register 4 - F2BAR4 (R/W)

Reset Value: 00000001h

Base Address 0 Register. This register allows access to I/O mapped Bus Mastering IDE registers. Bits [3:0] are read only (0001), indi-

cating a 16-byte I/O address range. Refer to Table 6-36 on page 277 for the IDE controller register bit formats and reset values.

31:4

Bus Mastering IDE Base Address.

3:0

Address Range. (Read Only)

Index 24h-2Bh

Reserved

Reset Value: 00h

Index 2Ch-2Dh

Subsystem Vendor ID (RO)

Reset Value: 100Bh

Index 2Eh-2Fh

Subsystem ID (RO)

Reset Value: 0502h

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