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SC3200 Datasheet(PDF) 317 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 317 Page - Advanced Micro Devices |
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317 / 447 page ![]() AMD Geode™ SC3200 Processor Data Book 317 Core Logic Module - ISA Legacy Register Space Revision 5.1 I/O Port 0D2h Software DMA Request Register, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. 7:3 Reserved. Must be set to 0. 2 Request Type. 0: Reset. 1: Set. 1:0 Channel Number Request Select. 00: Illegal. 01: Channel 5. 10: Channel 6. 11: Channel 7. I/O Port 0D4h DMA Channel Mask Register, Channels 7:4 (WO) Note: Channels 5, 6, and 7 are not supported. 7:3 Reserved. Must be set to 0. 2 Channel Mask. 0: Not masked. 1: Masked. 1:0 Channel Number Mask Select. 00: Channel 4. 01: Channel 5. 10: Channel 6. 11: Channel 7. I/O Port 0D6h DMA Channel Mode Register, Channels 7:4 (WO) Note: Channels 5, 6, and 7 are not supported. 7:6 Transfer Mode. 00: Demand. 01: Single. 10: Block. 11: Cascade. 5 Address Direction. 0: Increment. 1: Decrement. 4 Auto-initialize. 0: Disabled 1: Enable 3:2 Transfer Type. 00: Verify. 01: Write transfer (I/O to memory). 10: Read transfer (memory to I/O). 11: Reserved. 1:0 Channel Number Mode Select. 00: Channel 4. 01: Channel 5. 10: Channel 6. 11: Channel 7. Channel 4 must be programmed in cascade mode. This mode is not the default. I/O Port 0D8h DMA Clear Byte Pointer Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. I/O Port 0DAh DMA Master Clear Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. I/O Port 0DCh DMA Clear Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. Table 6-43. DMA Channel Control Registers (Continued) Bit Description |
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