SC3200 datasheet(322/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Core Logic Module - ISA Legacy Register Space

Revision 5.1

IRQ2 / IRQ10 Mask.

0: Not Masked.

1: Mask.

IRQ1 / IRQ9 Mask.

0: Not Masked.

1: Mask.

IRQ0 / IRQ8 Mask.

0: Not Masked.

1: Mask.

I/O Port 020h / 0A0h

Master / Slave PIC OCW2 (WO)

7:5

Rotate/EOI Codes.

000: Clear rotate in Auto EOI mode

100: Set rotate in Auto EOI mode

001: Non-specific EOI

101: Rotate on non-specific EOI command

010: No operation

110: Set priority command (bits [2:0] must be valid)

011: Specific EOI (bits [2:0] must be valid)

111: Rotate on specific EOI command

4:3

Reserved. Must be set to 0.

2:0

IRQ Number (000-111).

I/O Port 020h / 0A0h

Master / Slave PIC OCW3 (WO)

Reserved. Must be set to 0.

6:5

Special Mask Mode.

00: No operation.

01: No operation.

10: Reset Special Mask Mode.

11: Set Special Mask Mode.

Reserved. Must be set to 0.

Reserved. Must be set to 1.

Poll Command.

0: Disable.

1: Enable.

1:0

00: No operation.

01: No operation.

10: Read interrupt request register on next read of Port 20h.

11: Read interrupt service register on next read of Port 20h.

I/O Port 020h / 0A0h

Master / Slave PIC Interrupt Request and Service Registers

for OCW3 Commands (RO)

The function of this register is set with bits [1:0] in a write to 020h.

Interrupt Request Register

IRQ7 / IRQ15 Pending.

0: Yes.

1: No.

IRQ6 / IRQ14 Pending.

0: Yes.

1: No.

IRQ5 / IRQ13 Pending.

0: Yes.

1: No.

IRQ4 / IRQ12 Pending.

0: Yes.

1: No.

Table 6-46. Programmable Interrupt Controller Registers (Continued)

Bit

Description

SC3200 Datasheet(PDF) 322 Page - Advanced Micro Devices

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