AM79C850 datasheet(23/97 Pages) AMD

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P R E L I M I N A R Y

AMD

SUPERNET 3

Transmit Queues

ASYNC2 Transmit Queue Not Supported

The SUPERNET 3 supports SYNCHRONOUS, and two

ASYNCHRONOUS priorities. The ASYNC2 queue is no

longer supported. This causes the following changes:

1. TPRI2 (16-bit priority register for asynchronous

queue 2) is no longer implemented.

2. EAA2, WPXA2, SWPXA2, RPXA2 registers are no

longer implemented.

3. The ‘Clear Asynchronous Queue 2 Lock’ and

‘Transmit Asynchronous Queue 2’ commands are

no longer available in the command registers 1 and

2, respectively. The value 0x18 in command register

1 and 0x08 in command register 2 shall not be

decoded to any other instruction. These values are

reserved.

4. The STEFRMA2, STECFRMA2 and STXABRA2

bits in the upper 16 bits of the status register 1

(ST1U) are reserved and set to zero. Similarly

SQLCK2, STXINFLA2, SPCEPDA2, and STBURA2

are reserved and set to zero.

5. The QCTRL[2:0] = 100 encoding is now invalid. This

encoding

indicated

‘Request

transfer

into

Asynchronous Queue 2’ which is no longer

available. The encoding is reserved and shall not be

used to indicate any other QCTRL condition. (See

NOTE)

6. The HSREQ[2:0] = 111 is now decoded as “Write

Request: Asynchronous Queue 1”. In FORMAC+

this

request

indicated

write

request

asynchronous queue 2 which is no longer available.

Note: If the encoding HSREQ[2:0] = 111 is used, the

SUPERNET 3 would not use the QCTRL[2:0] = 100

encoding to indicate status of Asynchronous Queue, but

instead the QCTRL[2:0] = 011 (“Request transfer into

Asynchronous Queue 1”) encoding would be indicated

by SUPERNET 3 and external logic could be added to

invert this encoding to be compatible with FORMAC+.

AFULL Encoding of QCTRL Signals Modified

The QCTRL2–0 pins provide the encoded status of the

buffer memory transmit queues. The value QCTRL[2:0]

= 111, ‘Current queue almost full’, was asserted for one

host write cycle in SUPERNET 2. This signal shall now

be generated for every host write cycle until the queue

becomes full or the almost full threshold is no

longer exceeded.

This new signal assertion is implemented only if the bit

MENAFULL is set in mode register 3 (MDREG3)

Transmit Frame Format

In SUPERNET 2 transmit frames must consist of

aligned data, i.e. all words in the buffer memory must

contain four valid bytes, except that the last data word

may consist of less than four bytes. This required that

the Frame Control (FC) of the frame be written as the

most significant byte of the frame data long word.

SUPERNET 3 would support an enhanced feature,

where in the Frame Control (FC) could be any byte of the

frame data long word. The Destination Address (DA)

would follow the FC as the next byte in any mode of

operation. This feature is enabled only when the bits

MENFCLOC (bit 12 & 13) is set in mode register 3

(MDREG3). Upon reset these bits would be both zero

and the Frame Control (FC) has to be written as the

most significant byte of the frame data long word. The

following

table

describes

the

decoding

the

MENFCLOC bits in the mode register 3 (MDREG 3):

If MENFCLOC 13-12 =

Case 1: LSB = 0

Then FC starts at:

Byte 1

Byte 2

Byte 3

Byte 4

(MDREG 2 bit 11)

(MSBYTE)

(LSBYTE)

Case 1: LSB = 1

Then FC starts at:

Byte 4

Byte 3

Byte 2

Byte 1

(MDREG 2 bit 11)

(MSBYTE)

(LSBYTE)

AM79C850 Datasheet(PDF) 23 Page - Advanced Micro Devices

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