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AM79C850 Datasheet(PDF) 70 Page - Advanced Micro Devices

Part # AM79C850
Description  SUPERNET-R 3
PDF  97 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C850 Datasheet(HTML) 70 Page - Advanced Micro Devices

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AMD
P R E L I M I N A R Y
70
SUPERNET 3
SUPERNET 3 Programmable Registers (continued)
Register
Mnemonic
NPADDR7–0
Description
“pri1”
“1d”
Priority register for ASYNC1
“pri2”
“1e”
Reserved
“tsync”
“1f”
TSYNC register
“mod2”
“20”
Mode register 2
“frmthr”
“21”
Frame threshold register
“eacb”
“22”
End Address of Claim/Beacon area
“earv1”
“23”
End Address of receive queue
“eas”
“24”
End Address of synchronous queue
“eaa0”
“25”
End Address of asynchronous queue 0
“eaa1”
“26”
End Address of asynchronous queue 1
“eaa2”
“27”
Reserved
“sacl”
“28”
Start Address of Claim frame
“sabc”
“29”
Start Address of Beacon frame
“wpxsf”
“2a”
Write pointer for special frames
“rpxsf”
“2b”
Read pointer for special frames
“rpr1”
“2d”
Read Pointer for receive queue
“wpr1”
“2e”
Write pointer for receive queue
“swpr1”
“2f”
Shadow write pointer for receive queue
“wpxs”
“30”
Write pointer for synchronous queue
“wpxa0”
“31”
Write pointer for asynchronous queue 0
“wpxa1”
“32”
Write pointer for synchronous queue 1
“wpxa2”
“33”
Reserved
“swpxs”
“34”
Shadow write pointer for synchronous queue
“swpxa0”
“35”
Shadow write pointer for asynchronous queue 0
“swpxa1”
“36”
Shadow write pointer for asynchronous queue 1
“swpxa2”
“37”
Reserved
“rpxs”
“38”
Read pointer for synchronous queue
“rpxa0”
“39”
Read pointer for asynchronous queue 0
“rpxa1”
“3a”
Read pointer for asynchronous queue 1
“rpxa2”
“3b”
Reserved
“marr”
“3c”
Memory read address register
“marw”
“3d”
Memory write address register
“mdru”
“3e”
Upper 16 bits of memory data register
“mdrl”
“3f”
Lower 16 bits of memory data register
“tmsync”
“40”
TMSYNC register



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