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AM79C850 Datasheet(PDF) 41 Page - Advanced Micro Devices |
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AM79C850 Datasheet(HTML) 41 Page - Advanced Micro Devices |
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41 / 97 page ![]() P R E L I M I N A R Y AMD 41 SUPERNET 3 BSR Cell No. Pin No. Pin Type Description 207 30 output npmemack 208 32 output ready (oecell –1 to force 0, 0 to disable) 209 33 input r/ w 210 34 input ds 211 35 input csi 212 36 input lsclk 213 37 input npa[7] 214 38 input npa[6] 215 39 input npa[5] 216 40 input npa[4] 217 41 input npa[3] 218 42 input npa[2] 219 43 input npa[1] 220 44 input npa[0] 221 45 input npmode 222 46 input rst Built-In Self Test (BIST) The BIST feature of the SUPERNET 3 is provided to ease board and system level testing, as well as our own manufacturing testing. This feature can be accessed through the TAP as well as the system interface. It is expected that board level testing will use the TAP interface, while system level testing will not have access to the TAP interface and will need to run BIST through the system interface. There are two functional units in the SUPERNET 3 that are tested with BIST. These are the AF CAM core and the enhanced PHY. The BIST testing of the two functional units is available through the node processor interface. See the AF specification for a description of how to run the BIST for the AF. The enhanced PHY BIST is run using the PHY BIST access as described in the SUPERNET 2 PLC data sheet. Function BIST Signature (hex) Internal PLC BIST 5B6B Address Filter BIST 0553 SCANBIST 1 5B6B 0553 DISCRY function no longer supported Setting the DISCRY bit in mode register 1 (MDREG1, bit 6) permitted testing the operation of certain internal timers such as TRT, THT, TVX, and TMSYNC by breaking them into smaller segments. With the enhanced testability features of SUPERNET 3, the DISCRY function is no longer provided. The bit 6 of mode register 1 (MDREG1) is reserved and shall return a value of zero when read. Summary of Changes to Status and Mode Registers The following is the summary of changes. The bits in the register which are shaded indicate change from SUPERNET 2. All reserved bits shall be read as zero except where noted. |
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