AM79C850 datasheet(32/97 Pages) AMD

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AMD

P R E L I M I N A R Y

SUPERNET 3

RECV2 UNLOCK

THRESHOLD

LSB

MSB

19574A-5

RECV1 UNLOCK

THRESHOLD

Figure 4. Delay Register (UNLCKDLY)

Symbol Control

The SUPERNET 3 no longer supports the ability to

transmit raw symbols from the Buffer Memory to the

PHY. This feature has been removed and the mode bit

SYMCTL (bit 5, MDREG2) is now reserved and read

as zero.

Dual Attachment Station (DAS) support

The SUPERNET 3 is a SAS only device which is

extensible to a DAS configuration. For a DAS implemen-

tation, the MENDAS bit of the MDREG3 must be set and

the external PHY must be present. In a SAS

configuration, the R9:0 lines are tied to ground and X9:0

lines are driven at all times. The following configurations

are supported:

CFM

State

Figure

Description

Thru_A

Figure 5

The internal PHY is the A-port

and the external PHY is the

B-port. The MAC is placed as

shown in the figure. The MEN-

DAS bit in the MDREG3 must

be set.

Wrap_A

Figure 6

The internal PHY is the A-port

and the external PHY is the

B-port which must be in BYPASS

(if PLC). The MAC is placed as

shown in the figure. The MEN-

DAS bit in the MDREG3 must

be set.

Wrap_B

Figure 7

The internal PHY is the A-port

which must be in BYPASS and

the external PHY is the B-port.

The MAC is placed as shown in

the figure. The MENDAS bit in

the MDREG3 must be set.

Wrap_S

Figure 8

This is the default configuration

of the SUPERNET 3. No external

PHY is required. The MENDAS

bit in the MDREG3 must be reset

(by default). This decouples the

busses from the external PHY as

shown in the figure.

Isolated

The internal PHY (A-port) and

the external PHY (B-port) are

isolated. This is the default reset

state.

Thru_B

This configuration is not

supported.

AM79C850 Datasheet(PDF) 32 Page - Advanced Micro Devices

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