AM79C850 datasheet(28/97 Pages) AMD

28 / 97 page

AMD

P R E L I M I N A R Y

SUPERNET 3

Address Space

The FORMAC Plus uses seven pins (0–6) and the PLC

uses five pins (0–4). The new address space uses eight

pins (0–7) with the following decoding:

Address 7:0

Comment

00–7F

MAC addresses. Up to 128 addresses can

be accessed. Currently 127 addresses are

used. Full backward compatibility

80–AF

PHY addresses. Currently the PLC has

28 registers defined. This would allow up

to 48 addresses to be accessed

B0–CF

Address Filter (AF) addresses. Note that

the AF currently has ten addresses all of

which are read /written by the user

D0–DF

PDX address space. There are 16 possible

addresses.

E0–FF

Reserved for future use

Interrupts

There are four interrupts: two for the MAC, one for the

MAC/BIST, and one for the PHY. The two interrupts for

the MAC ensure that the interrupt service routine (ISR)

does not have to perform two reads to determine which

of the status registers generated the interrupt. The third

interrupt is generated when the BIST operations are

complete or when the second receive queue has

changes in its status. The fourth interrupt indicates the

status of the PHY.

Interrupt Mechanisms

SCALAR: There are four interrupts, two from MAC, one

from MAC and BIST, and one

from PHY. These

interrupts can be tied together externally or serviced

separately. This method is the default and is backwards

compatible with the SUPERNET 2 interrupt generation

and servicing mechanisms.

VECTORED:

Only

one

interrupt

monitored

(MINTR4), and upon an interrupt being generated, a

16-bit maskable Interrupt Vector Register (IVR) is read.

Each bit in the vector register indicates the source of the

interrupt. The vector register bits are:

Bits

Interrupt Source

bit 0

MAC Status register 1 Upper (ST1U)

bit 1

MAC Status register 1 Lower (ST1L)

bit 2

MAC Status register 2 Upper (ST2U)

bit 3

MAC Status register 2 Lower (ST2L)

bit 4

MAC Status register 3 Upper (ST3U)

bit 5

MAC Status register 3 Lower (ST3L)

bit 6

PHY Interrupt Event register

(INTR_EVENT)

bit 7–15

Reserved. Shall be read as zero.

This method of interrupt generation and processing can

be enabled by setting the MENSGLINT (bit 10) in the

mode register 3 (MDREG3). If enabled, this mechanism

requires the user to read the Interrupt Vector Register

(IVR), locate the bit which is set, and read the

corresponding interrupt event or status register. Each

bit in the IVR is maskable. The interrupts can be

unmasked by setting the corresponding bit in the

Interrupt Mask Register (IMR). By default, all bits in the

IMR are reset (to zero) and all interrupts are masked.

The mask register bits are:

Bits

Interrupt Source

bit 0

Mask MAC Status register 1 Upper (ST1U)

interrupt.

bit 1

Mask MAC Status register 1 Lower (ST1L)

interrupt.

bit 2

Mask MAC Status register 2 Upper (ST2U)

interrupt.

bit 3

Mask MAC Status register 2 Lower (ST2L)

interrupt.

bit 4

Mask MAC Status register 3 Upper (ST3U)

interrupt

bit 5

Mask MAC Status register 3 Lower (ST3L)

interrupt.

bit 6

PHY Interrupt Event register

(INTR_EVENT) interrupt.

bit 7–15

Reserved. Shall be read as zero.

Once MINTR4 is activated, the corresponding status or

event register must be read to enable any further

interrupt on MINTR4.

Receive Flush/Transmit Inhibit pin

FLXI (input)

The HOFLXI pin is now the FLXI pin and the HOLD

function is no longer supported. The functional timing for

this pin is as specified in the SUPERNET 2 data book.

If the FLUSH function is selected and the pin is asserted

by external logic, then the incoming frame is flushed.

The buffer memory pointers are not advanced from

where they were before the frame was received (i.e.

WPR = SWPR). The receive flush pin is asserted by the

host to flush the current frame being received based on

an external criterion regardless of the address match.

This prevents unwanted frames and fragments from

occupying receive buffer space and taking up the buffer

memory bus bandwidth. If receive threshold is non-zero,

then the frame will be flushed only if the pin is asserted

before the threshold is crossed. Refer to timing diagram

for details.

If the TRANSMIT INHIBIT function is selected and

the pin is asserted by external logic, then the

SUPERNET 3 completes transmitting the current frame

AM79C850 Datasheet(PDF) 28 Page - Advanced Micro Devices

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