AM79C850 datasheet(12/97 Pages) AMD

12 / 97 page

AMD

P R E L I M I N A R Y

SUPERNET 3

high, the upper nibble of the X-bus is interpreted as a

network control character. Otherwise, it is interpreted as

a data nibble.

XCL

Transmit Control Lower (TTL output, high

impedance)

The XCL output signal is used to flag control symbols

being presented on the lower nibble of the transmit bus.

This signal is synchronous to BCLK. If XCL is asserted

high, the lower nibble of the X-bus is interpreted as a

network control character. Otherwise, it is interpreted as

a data nibble.

FOTOFF

Fiber Optic Transmitter Off (TTL Output, Active

Low, high impedance)

The

FOTOFF signal, when asserted, causes the optical

transmitter to turn off.

SDI+, SDI-

Signal Detect (PECL Differential Line Receiver

Inputs)

The SDI input signal pair is from the optical or copper

transceivers to indicate whether the received optical or

electrical signal is above its threshold. The inverted

value of this signal is held in the PHY_STATUS_A

whenever SDI becomes asserted.

SCRM

Scrambler/Descrambler enable (DC Input,

Active High)

When this pin is strapped high, the SUPERNET 3 is set

to operate with a copper PMD and the scrambler/

descrambler is enabled. When the pin is strapped to

ground, then the scrambler/descrambler function is

disabled in the SUPERNET 3, and the SUPERNET 3 is

set to operate with a fiber PMD. This pin is ORed with

the bit 0 (CIPHER_ENABLE) in the PLC_CNTRL_C

The PMD selection and scrambler/descrambler (S/D)

enabling is as follows:

CIPHER_

SCRM

ENABLE

bit

Result

Low

Reset

Fiber PMD. S/D disabled.

Low

Set

Copper PMD. S/D enabled.

High

Reset

Copper PMD. S/D enabled.

High

Set

Copper PMD. S/D enabled.

LSR 2–0

Line State Register (TTL Output, high impedance)

The LSR2–0 signals directly output the LINE_ST field

of the PLC_STATUS_A register to ring test and

monitor equipment.

EBFERR

Elasticity Buffer Error (TTL Output, Active High,

high impedance)

EBFERR indicates when an overflow or underflow

condition occurs in the Elasticity Buffer.

ENCOFF

Encoder Off (TTL Input, Active High)

ENCOFF signal turns off the 4B/5B encoding and

decoding function of the PLC core.

ULSB

Unknown Line State (TTL Output, high impedance)

The ULSB signal directly outputs the UNKN_LINE_ST

bit of the PLC_STATUS_A register to ring test and

monitor equipment.

Clock Pins (3 Pins)

LSCLK

Local Symbol Clock pin (TTL input)

The LSCLK is a 25 MHz clock. It is used by the

PLC core.

BCLK

Byte Clock pin (TTL input)

The BCLK is a 12.5 MHz clock. It is used by the PLC and

the MAC cores.

BMCLK

Buffer Memory Clock pin (TTL input)

The BMCLK is the clock signal that the MAC core uses

for generating the signals to the buffer memory. BMCLK

is driven with either a 12.5 or 25 MHz clock signal. If

12.5 MHz operation is desired, then this pin can be tied

to BCLK pin. If 25 MHz operation is desired, then this pin

can be tied to LSCLK pin.

Node Processor (NP) Interface

(35 Pins)

The following paragraphs describe the pins used to

interface the SUPERNET 3 with the node processor

(NP) or other control devices. The NP interface is used

for initializing the SUPERNET 3 as well as for

reporting status.

CSI

Chip Select Input (TTL input, active low)

– Asynchronous when NPMODE = 0

– Synchronous when NPMODE = 1

The Chip Select Input (active low) enables Read and

Write operations to the SUPERNET 3. In the asynchro-

nous mode, the data output is enabled while

CSI and DS

are both low and R/

W is high. In the synchronous mode,

the data output is enabled while

CSI is low and R/W

is high.

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