AM79C850 datasheet(36/97 Pages) AMD

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AMD

P R E L I M I N A R Y

SUPERNET 3

Instructions Supported

This section describes the public and private instruc-

tions that are supported in this implementation. The

instruction register is a 4-bit register. The least

significant bit of the instruction register is the bit nearest

the TDO output. The encoding of the instructions is

as follows:

Instruction

Description

Reg. Selected

INST[3:0]

EXTEST

External test

B.S.R.

0000

IDCODE

Device identification

IDREG

0001

SAMPLE

Sample/preload B.S.R.

B.S.R.

0010

TRI_ST

Force outputs to Hi-Z

Bypass

0011

RUNBIST

Self-test

BIST Execution

0101

SCANBIST

Manufacturing Testing

Scan Results

0110

BYPASS

Bypass register scan

Bypass

1111

EXTEST Instruction

The EXTEST instruction is used to test board level

interconnect and for testing of circuitry external to

SUPERNET 3. This instruction selects the Boundary

Scan register (BSR) for scanning between TDI and TDO

when in the Shift-DR controller state. During execution:

1. SUPERNET 3 outputs are driven from the Parallel

Data register (PDR).

2. SUPERNET 3 internal outputs are sampled into the

BSR.

3. SUPERNET 3 inputs are sampled into the BSR.

4. SUPERNET 3 internal inputs are driven from the

Parallel Data register (PDR).

IDCODE Instruction

The IDCODE instruction is provided for access to the

manufacturer’s identity, the part number, and the

version of the SUPERNET 3. This instruction selects the

32-bit identification register for scanning between TDI

and TDO in the Shift-DR controller state. The IDCODE

instruction is forced into the instruction registers parallel

output latches during the Test-Logic-Reset controller

state. The 32 bits of the identification register are broken

down as follows:

Bits

Description

IDREG[31:28]

Version number (initially 0001)

IDREG[27:12]

Part number - 2870 (Hex)

IDREG[11:1]

Manufacturer’s ID. The 11-bit

manufacturer’s ID. for AMD is

00000000001 according to JEDEC

publication 106-A.

IDREG[0]

Always set to logic 1.

IDREG[31:0]

Value = 1287 0003 (Hex)

SAMPLE Instruction

The SAMPLE/PRELOAD instruction is used to observe

the normal operation of the SUPERNET 3 without

affecting system operation. It is also used to load values

into the PDR prior to the selection of another instruction.

This instruction selects the BSR for scanning between

TDI and TDO during the Shift-DR controller state.

During execution:

1. SUPERNET

outputs

are

driven

the

SUPERNET 3.

2. SUPERNET 3 internal outputs are sampled into the

BSR.

3. SUPERNET 3 inputs are sampled into the BSR.

4. SUPERNET 3 internal inputs are driven from the

SUPERNET 3 inputs.

TRI_ST Instruction

The TRI_ST instruction is provided for easy tri-state of

all SUPERNET 3 outputs. This instruction selects the

bypass register for scanning between TDI and TDO

during the Shift-DR controller state.

RUNBIST Instruction

The RUNBIST instruction is provided for self-test of the

SUPERNET 3. This instruction must not be selected

during the normal operation of the part.

Once the RUNBIST instruction is selected, the BIST

operation is enabled by applying a minimum of 65000

TCK clock cycles while in the RUN-TEST/IDLE TAP

controller state. Once the minimum number of clock

cycles

have

elapsed,

proceed

load

the

SCANBIST instruction.

SCANBIST Instruction

The SCANBIST instruction selects the BIST result

Shift-DR controller state. The BIST results can be

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