PC8374L datasheet(207/239 Pages) NSC

207 / 239 page

9.0 Legacy Functional Blocks (Continued)

Revision 1.1

207

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The default bank selection after system reset is 0.

Figure 40. Register Bank Architecture

Table 93 shows the main functions of the registers in each bank. Banks 0-3 control both UART and IR modes of operation;

banks 4-7 control and configure the IR modes only.

Table 93. Register Bank Summary

9.5.3

SP2 Register Map

All registers are VDD3 powered.

Bank UART Mode

IR Mode

Main Functions

✓✓

Global Control and Status

✓✓

Legacy Bank

✓✓

Alternative Baud Generator Divisor, Extended Control and Status

✓✓

Module Revision ID and Shadow registers

✓

IR mode setup

✓

IR Control

✓

IR Physical Layer Conﬁguration

✓

CEIR and Optical Transceiver Conﬁguration

Table 94. Bank 0 Register Map

Offset

Mnemonic

Type

00h

RXD

Receiver Data

TXD

Transmitter Data

01h

IER

Interrupt Enable

R/W

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

Offset 07h

Offset 06h

Offset 05h

Offset 04h

LCR/BSR

Offset 02h

Offset 01h

Offset 00h

Common

Throughout

All Banks

16550 Banks

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PC8374L Datasheet(PDF) 207 Page - National Semiconductor (TI)

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